`timescale 1ns/1ps
module 	pc(	//input
				clk,
				nrst,
				rxd,
				
			//output
				txd,
				jud_err
				);
				
//`include "../script.v"
input			clk,
				nrst,
				rxd;
				
output			txd;
output   [7:0]  jud_err; //judge the  8channel data whether right or not   

reg				en_tx;
reg		[7:0] 	data_tx	;
//reg				baud = 1'b1;//boud rate is 115200;
 reg             baud = 1'b0;//boud rate is 19200

wire			txd,
				rdc,
				tdc;
wire [7:0]	data_rx;
reg  [7:0]  jud_err;				


task pc_testbegin;
begin
	pc_cmd(8'h21);
	pc_cmd(8'h00);
	pc_cmd(8'h01);
	pc_cmd(8'h21);
	
end
endtask


			
task pc_init;
begin
	pc_cmd(8'h20);
	pc_cmd(8'h00);
	pc_cmd(8'h01);
	pc_cmd(8'h20);
end
endtask


task	pc_cmd;
input	[7:0]	data_cmd;
begin
	repeat(2)@(posedge clk);
	@(posedge clk)	data_tx <= data_cmd;
	@(posedge clk)  en_tx <= 1; 
	@(posedge clk)	en_tx <= 0;
	repeat(2)@(posedge clk);
	@(posedge tdc) ;
	repeat(2)@(posedge clk);
	$display("[NOTE:] @ %t %h has been transmit", $time, data_cmd);
end
endtask

task pc_rec_one_byte; //PC机接收过来的数据
output [7:0] buff;
	begin : rece_data 
		forever@(posedge clk)
		begin
		    if(rdc)
			begin 
				buff <= data_rx;
				#1 disable rece_data;
			end
		end
	end
endtask	


task recv_init ;
reg [7:0] data;
	integer i;	
	begin:asd 
		pc_rec_one_byte(data);
		if(data != 8'h20)
		begin
			$display("[ERROR:] @%t the start of the init  %h is not 8'h20", $time, data);
			$finish;
			disable recv_jude;
		end		
		pc_rec_one_byte(data);
		if(data != 8'h00)
		begin
			$display("[ERROR:] @%t the second of the init  %h is not 8'h00", $time, data);
			$finish;
			disable recv_jude;
		end				
		pc_rec_one_byte(data);
		if(data != 8'h08)
		begin
			$display("[ERROR:] @%t the third of the init  %h is not 8'h08", $time, data);
			$finish;
			disable recv_jude;
		end				  				  
		for(i = 0; i < 8; i = i+1)
			begin
			pc_rec_one_byte(data);
				if( data[7] == 1 )
				begin
					jud_err[i] <= 1;
					$display("[buff:] @%t the channel %d data is init", $time, data[3:0]);
				end
				else
				begin
					jud_err[i] <= 0;
					$display("[buff:] @%t the channel %d data is init", $time, data[3:0]);
				end
			end					  							
	end
endtask


task recv_jude ;
reg [7:0] data;
	integer i;	
	begin:asd 
		pc_rec_one_byte(data);
		if(data != 8'h21)
		begin
			$display("[ERROR:] @%t the start of the data  %h is not 8'h21", $time, data);
			$finish;
			disable recv_jude;
		end		
		pc_rec_one_byte(data);
		if(data != 8'h00)
		begin
			$display("[ERROR:] @%t the second of the data  %h is not 8'h00", $time, data);
			$finish;
			disable recv_jude;
		end				
		pc_rec_one_byte(data);
		if(data != 8'h08)
		begin
			$display("[ERROR:] @%t the third of the data  %h is not 8'h08", $time, data);
			$finish;
			disable recv_jude;
		end				  				  
		for(i = 0; i < 8; i = i+1)
			begin
			pc_rec_one_byte(data);
				if( data[7] == 1 )
				begin
					jud_err[i] <= 1;
					$display("[buff:] @%t the channel %d data is wrong", $time, data[3:0]);
				end
				else
				begin
					jud_err[i] <= 0;
					$display("[buff:] @%t the channel %d data is right", $time, data[3:0]);
				end
			end					  							
	end
endtask 
 

task pc_script;
	begin
	/*********64位固定信息位*********/
	pc_cmd(8'h0e);
	pc_cmd(8'h09);
	pc_cmd(8'h00);
	pc_cmd(8'h00);
	/********128固定信息位**********/
	pc_cmd(8'h00);
	pc_cmd(8'h00);
	pc_cmd(8'h00);
	pc_cmd(8'h00);
	pc_cmd(8'h00);
	pc_cmd(8'h00);
	end
endtask
				
				
uart_tb	u_uartpc(.clk(clk),
				.nrst(nrst),
				.en_tx(en_tx),			//start to tx//the data need to send
				.rxd(rxd),
				.din(data_tx),			//data which used to tx
				.baud_set(baud),		//set baud
				//out
				.txd(txd),
				.error(),
				.rdc(rdc),				//rx data completed
				.tdc(tdc),				//tx data completed
				.data(data_rx)			//receive data from rx
				);
endmodule	
